In the fabrication of integrated circuitry, masks may be used when etching into underlying material to form desired feature shapes. Photolithographic processing is one technique used in fabrication of such masks. For example, photoresist may be deposited over a substrate and exposed to patterned radiation followed by developing to form a patterned photoresist mask. The pattern of the photoresist mask may be subsequently transferred to form electronic device components into underlying substrate material that is one or more of electrically conductive, insulative, or semiconductive. In many applications, the photoresist material of the mask is insufficiently robust by itself to serve as a mask while completing etching of the device features. Hardmask material may be used in such instances between the photoresist and the material into which the device features are formed. Accordingly, the photoresist mask pattern is transferred into the hardmask material which is then used as a more robust etching mask than photoresist. In such instances, the photoresist is likely completely removed during etch of the hardmask material or during etch of the material beneath the hardmask material.
Integrated circuitry fabrication continues to make ever smaller feature width dimensions to minimize the size of individual device components and thereby increase density of the components within an integrated circuit. One common component in integrated circuits is an electrically conductive line, for example global or local interconnect lines. Other example conductive lines include transistor gate lines that may or may not incorporate charge storage regions which are spaced along individual transistor gate lines. When etching conductive material beneath a hardmask to form conductive lines, it is desirable that the line material have sidewalls which correspond to the longitudinal orientation of the sidewalls of the patterned hardmask material. However, as minimum line widths approached 30 nanometers, the etching may have a tendency to form the line sidewalls that serpentine in a wave-like manner along the longitudinal orientation of the lines. This may not be desirable.
For example referring to FIG. 1, a top view of a portion of a prior art substrate 10 is shown. Such includes plurality of line constructions 14 which have been patterned over underlying substrate material 12. Line constructions 14 were formed using pitch multiplication techniques wherein minimum width of individual of the lines was about 25 nanometers, and space between immediately adjacent of the lines was about 30 nanometers. A sacrificial hardmask material (not shown) comprising a compressive amorphous carbon layer received over a compressive undoped silicon dioxide layer was used as spaced line features of a mask. Such resulted in the depicted undesired line waviness of the sidewalls along the longitudinal orientation of the lines.
While the invention was motivated in addressing the above-identified issues, the invention is in no way so limited. Rather, the invention is limited by the accompanying claims as appropriately interpreted in accordance with the doctrine of equivalence.